502 is basically a conventional general-purpose computer having storage, arithemtic, input, output and control facilities. The arrangement of the basic machine is shown in Fig. 1, and consists of the following components.
|A is the 20-bit Accumulator|
|R is the 20-bit Auxiliary Register|
|B is the 20-bit Modifier Register|
|S is the 20-bit Sequence Control Register|
The Accumulator contains one of the two operands involved in all arithmetical functions.
The Auxiliary register is used in conjunction with teh Accumulator when double-length numbers are encountered in multiplication and division.
The Modifier Register may be used to hold numbers for the automatic modification or indexing of instructions as required by the programmer. The use of this and other registers for modifying instructions is explained further below in the description of the Index bits in the instructions.
The Sequence Control Register holds a number which specifies the address of the next instruction to be obeyed, the sign bit indicating whether this address refers to the fast store or the main store. Although readily available to the programmer, this bit can only be changed by a jump instuction.
The Count has two six-bit registers and a subtracting mechanism. It operates simultaneously with the Function Unit to speed up the Group 6 instructions.
Subsequently the content of G is gated back into, say, one of the registers.
Provision is made in the timing mechanism for lengthening or shortening either part of the operation according to the functoion being performed, to achieve maximum speed.
|1 bit||1 bit||6bits||2 bits||10 bits|
|S||This bit, when present in an instruction prevents any interruption taking place until the succeeding instruction has been obeyed.|
|M||This bit is known as the Store Mode bit.
|F||The function group contains two octal digits specifying the operation to be performed. The available operations are classified in eight groups of eight, as detailed in the instruction code which is given below.|
|K||The Index bits K specify the source of the modifier to be added
to the instruction before it is obeyed.
The Sequence Control Register always specifies the next location to be obeyed; thus if an instruction in location 100 is modified by the content of the Sequence Control Register, 101 is added to the address part of the instruction before it is obeyed. When the content of the Sequence Control Register is used as a modifier, the extra bit used to specify the store is ignored.
|N||The address bits are decoded in one of four possible ways, according to the function and store mode specified in the instructions. in all cases the specified modifier is added to the instrcution before it is obeyed.|
In Groups 0 and 1, when M = 0, N is used as an operand between 0 and 1023 x 2-19 and when M = 1, N specifies a main store address. Note that since the modifiers may be up to 20 bits long, the whole main store can be addressed in this way.
In Groups 2 and 3, when M = 0, N specifies the address of an operand in the fast store, and when M = 1, the contents of the fast store location specified by N is used to address an operand in the main store, a process known as indirect addressing.
Page created by Bill Purvis, last update: 20th November, 2003 include "../../count.php"; countPage("ccs_502_502.p8.html"); ?>