A BRIEF SPECIFICATION OF THE 502

Basic arragement

502 is basically a conventional general-purpose computer having storage, arithemtic, input, output and control facilities. The arrangement of the basic machine is shown in Fig. 1, and consists of the following components.

Fast core store

The fast core store is a ferrite magnetic core matrix system of a new and advanced design, with a capacity of 1024 words. Access time is less than 0.5 microseconds, and cycle time about one microsecond. There is an Access Register and an Address Register associated with this store.

Main core store

The main store is also of the magnetic core type, and is an improved system based upon conventional design. The capacity is 8192 words in the basic machine, but provision has been made for extension to capacities of 65536 words when required. Access time is less than 2.5 microseconds and cycle time is less than 5 microseconds. There is an Access Register and an Address Register associated with this store.

Function unit

The function unit contains a fast 20-bit adder/subtracter, and has facilities for collating, shifting and counting. A 22-bit Result Transfer Register G is associated with this unit, which is used for all arithmetical operations in the 502, including address sequencing and indexing.

Special registers

There are four register which are all implicitly addressable, in that they are available to the programmer, and which bear the reference letters A, R, B, and S.

A is the 20-bit Accumulator
R is the 20-bit Auxiliary Register
B is the 20-bit Modifier Register
S is the 20-bit Sequence Control Register

The Accumulator contains one of the two operands involved in all arithmetical functions.

The Auxiliary register is used in conjunction with teh Accumulator when double-length numbers are encountered in multiplication and division.

The Modifier Register may be used to hold numbers for the automatic modification or indexing of instructions as required by the programmer. The use of this and other registers for modifying instructions is explained further below in the description of the Index bits in the instructions.

The Sequence Control Register holds a number which specifies the address of the next instruction to be obeyed, the sign bit indicating whether this address refers to the fast store or the main store. Although readily available to the programmer, this bit can only be changed by a jump instuction.

The Count has two six-bit registers and a subtracting mechanism. It operates simultaneously with the Function Unit to speed up the Group 6 instructions.

Method of operation

In a typical arithmetical operation in the 502, the contentent of one of the registers and one word from a store are gated into the Function Unit, operated upon and transferred to G. For an operation involving a carry propagation (e.g. addition and subtraction) this takes about 0.3 microseconds. This time is shorter if there is no carry propagation.

Subsequently the content of G is gated back into, say, one of the registers.

The complete operation takes 0.4 microseconds

Provision is made in the timing mechanism for lengthening or shortening either part of the operation according to the functoion being performed, to achieve maximum speed.

Representation of numbers

Numbers in the 502 are normally held as signed binary fractions lying in the range -1 to +(1-2-19), negative numbers being represented by their twos complement.

Word length

20-bit words are used throughout the 502.

Instruction format

The single-address instructions occupy one word; ten bits are used for the address N, six for the function F, two in a group designated K, and two single bits designated S and M. The action of these groups is further described below, and the distribution of bits in the instruction words is as follows:
1 bit1 bit6bits2 bits10 bits
SMFKN
S This bit, when present in an instruction prevents any interruption taking place until the succeeding instruction has been obeyed.
M This bit is known as the Store Mode bit.
If M = 0, the address N may itself be an operand, or may be the address of an operand in the fast store.
If M = 1, the address N specifies ether the location of an operand in the main store, or the location in the fast store which holds the address of an operand in the main store. If the latter case the operand is said to be obtained by indirect addressing.
F The function group contains two octal digits specifying the operation to be performed. The available operations are classified in eight groups of eight, as detailed in the instruction code which is given below.
K The Index bits K specify the source of the modifier to be added to the instruction before it is obeyed.
If K = 0, no modification takes place.
If K = 1, the modifier is taken from the Modifier Register B.
If K = 2, the modifier is taken from the Accumulator, A.
If K = 3, the modifier is taken from the Sequence Control Register, S.

The Sequence Control Register always specifies the next location to be obeyed; thus if an instruction in location 100 is modified by the content of the Sequence Control Register, 101 is added to the address part of the instruction before it is obeyed. When the content of the Sequence Control Register is used as a modifier, the extra bit used to specify the store is ignored.

N The address bits are decoded in one of four possible ways, according to the function and store mode specified in the instructions. in all cases the specified modifier is added to the instrcution before it is obeyed.

In Groups 0 and 1, when M = 0, N is used as an operand between 0 and 1023 x 2-19 and when M = 1, N specifies a main store address. Note that since the modifiers may be up to 20 bits long, the whole main store can be addressed in this way.

In Groups 2 and 3, when M = 0, N specifies the address of an operand in the fast store, and when M = 1, the contents of the fast store location specified by N is used to address an operand in the main store, a process known as indirect addressing.

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Page created by Bill Purvis, last update: 20th November, 2003