In the following list the usual notation is used to specify data transfers. Capital letters are used to refer to registers, or to represent numerical values directly; lower case letters, and capitals in parenthesis, represent the content of registers. Note also the special usage, where
| N | is the direct operand | |
| (N) | is the content of location N in the main store | |
| n | is the content of location N in the fast store | |
| (n) | is the content of a main store address held in fast store location N. |
Primed symbols refer to the content of a register after the operation is completed.
Unless specified in the instruction, the content of a register remains unaltered.
| Function | M = 0 | M = 1 | ||
| Group 0 - Modifier setting instructions - direct and main store addresses | ||||
| 00 | b' = b + N | b' = b + (N) | ||
| 01 | b' = b - N | b' = b - (N) | ||
| 02 | b' = -b + N | b' = -b + (N) | ||
| 03 | b' = N | b' = (N) | ||
| 04 | b' = - | (N)' = b + (N) | ||
| 05 | b' = - | (N)' = b - (N) | ||
| 06 | b' = - | (N)' = -b + (N) | ||
| 04 | b' = - | (N)' = b | ||
| Group 1 - Short arithmetical instructions - direct and main store addresses | ||||
| 10 | a' = a + N | a' = a + (N) | ||
| 11 | a' = a - N | a' = a - (N) | ||
| 12 | a' = -a + N | a' = -a + (N) | ||
| 13 | a' = N | a' = (N) | ||
| 14 | - | (N)' = a + (N) | ||
| 15 | - | (N)' = a - (N) | ||
| 16 | - | (N)' = -a + (N) | ||
| 17 | - | (N)' = a | ||
| Group 2 - Modifier setting instructions - fast store and indirect access | ||||
| 20 | b' = b + n | b' = b + (n) | ||
| 21 | b' = b - n | b' = b - (n) | ||
| 22 | b' = -b + n | b' = -b + (n) | ||
| 23 | b' = n | b' = (n) | ||
| 24 | n' = b + n | (n)' = b + (n) | ||
| 25 | n' = b - n | (n)' = b - (n) | ||
| 26 | n' = -b + n | (n)' = -b + (n) | ||
| 27 | n' = b | (n)' = b | ||
| Group 3 - Short arithmetical instructions - fast store and indirect access | ||||
| 30 | a' = a + n | a' = a + (n) | ||
| 31 | a' = a - n | a' = a - (n) | ||
| 32 | a' = -a + n | a' = -a + (n) | ||
| 33 | a' = n | a' = (n) | ||
| 34 | n' = a + n | (n)' = a + (n) | ||
| 35 | n' = a - n | (n)' = a - (n) | ||
| 36 | n' = -a + n | (n)' = -a + (n) | ||
| 37 | n' = a | (n)' = a | ||
| The overflow marker is set if the result of any operation was outside the range -1 to +(1-2-19). | ||||
| Group 4 - Transfer control instructions | ||||
| Note: | The Sequence Control register contains an extra bit to specify whether the next instruction is to come from the fast store or the main store, and in all transfer control instructions, the mode bit is used to determine the value of this extra bit. If an address greater than 1023 is required, a modifier must be added. | |||
| 40 | Count up, if now b ≠ 0, | b' = b + 1 s' = N in fast store when M = 0,or in main store when M = 1 | ||
| 41 | Count down, if now b ≠ 0, | b' = b - 1 s' = N in fast store when M = 0, or in main store when M = 1 | ||
| 42 | Jump if B zero, if now b = 0, | s' = N in fast store when M = 0, or in main store when M = 1 | ||
| 43 | Sub-routine jump | b' = s s' = N in fast store when M = 0, or in main store when M = 1 | ||
| After this instruction the sign digit of B is zero is the instruction is in the fast store, one if it is in the main store | ||||
| 44 | Jump if positive or zero if a ≥ 0 | s' = N in fast store when M = 0, or in main store when M = 1 | ||
| 45 | Jump if negative if a < 0 | s' = N in fast store when M = 0, or in main store when M = 1 | ||
| 46 | Jump if zero if a = 0 | s' = N in fast store when M = 0, or in main store when M = 1 | ||
| 44 | Test overflow and jump if overflow marker is set | s' = N in fast store when M = 0, or in main store when M = 1 | ||
| and clear overflow marker | ||||
| No Group 4 instructions set the overflow marker. | ||||
| Group 5 - Miscellaneous instructions | ||||
| 50 | Jump s' = N in fast store when M = 0, or in main store when M = 1 | |||
| 51 | Jump backwards s' = s - N in fast store when M = 0, ir in main store when M = 1 s is the address of this instruction plus one | |||
| 52 | Collate to A a' = a & n if M = 0 a' = a & (N) if M = 1 This instruction gives a digit-by-digit logical conjunction of the content of the two registers | |||
| 53 | Send to R r' = n if M = 0 r' = (N) if M = 1 | |||
| 54 | Count up in store n' = n + 1 if M = 0 (N)' = (N)' + 1 | |||
| This order does not set the overflow indicator | ||||
| 55 | Count down in store n' = n - 1 if M = 0 (N)' = (N)' + 1 | |||
| This order does not set the overflow indicator | ||||
| 52 | Collate to store n' = a & n if M = 0 (N)' = a & (N) if M = 1 | |||
| 53 | R to store n' = r if M = 0 (N)' = r if M = 1 | |||
| Group 6 - Long arithmetical instructions and shifts | ||||
| Note: | On the use of the N bits in shift instructions | |||
| For shift instruction the address bits are used to signify a number N in the range | ||||
| -63≤N≤+63 | ||||
| where N is the number of places to be shifted to the left, and is obtained as follows. | ||||
| The ten least significant bits of the instruction are modified by the addition of the content of the specified index register. If in the result the 2-10 bit is zero, N is positive and is equal to the 6 least significant bits expressed as an integer. If the 2-10 bit is one, N is negative and its absolute value is equal to the six least significant bits of the twos complement of the modified address. In either case the correct shift is obtained even when a signed address is modified by a signed modifier. | ||||
| Note: | On double length functions | |||
| For the purposes of functions acting on double-length numbers AR is considered as one 39-bit register (38 bits plus sign). | ||||
| 60 | Logical shift Shift the contents of the Accumulator N places logically Overflow is not set by this instruction | |||
| 61 | Single-length arithmetical shift Shift the contents of the Accumulator N places arithmetically so that | |||
| a' = a x 2N | ||||
| Overflow is set if a' is outside the range -1 to +(1-2-19) | ||||
| 62 | Double-length arithmetical shifts. Shift the contents of the accumulator and auxiliary register together, considered as one double length register, N places arithmetically so that | |||
| [ar]' = [ar] x 2N | ||||
| Overflow is set if [ar]' is outside the range -1 to +(1-2-19) | ||||
| The most significant bit of R is cleared before the function commences but is otherwise ignored. | ||||
| 63 |
Square root a' = square root of(a + n) if M = 0 a' = square root of(a + (N)) if M = 1 R is cleared. If (a')2 is outside the range -1 to +(1-2-19), overflow is set. | |||
| 64 | Double length multiplication [ar]' = a x n if M = 0 [ar]' = a x (N) if M = 1 The Accumulator (A) and the Auxiliary register (R) together hold the correct product of two signed 19-bit fractions as one signed 38-bit fraction. The sign digit of R is cleared. Overflow is set if the product is +1 | |||
| 65 | Rounded multiplication a' = a x n if M = 0 a' = a x (N) if M = 1 The Accumulator contains the signed product rounded to single-length Accuracy. The Auxiliary register is cleared. | |||
| 66 | Division with remainder r' = quotient, a' = remainder in other words r' = [ar - (a'x2-19)]/n provided it is within the range -1 to +(1-2-19) This is for M = 0; for M = 1, n is replaced by (N) in the above expression. A and R together are considered as a signed 38-bit fraction; at the beginning of the operation. At the end R contains the signed quotient A the remainder. The sign of the remainder is the same as that of the original dividend. Overflow is set if the quotient is out of scale. | |||
| 67 | Rounded division a' = ar/n for M = 0 a' = ar/(N) for M = 1 A and R contain a signed 38-bit number as in order 66. The signed quotient in this case is put into A and rounded. The Auxiliary Register is cleared at the end of the operation. Overflow is set if the quotient is out of Scale. | |||
| Group 7 - Peripheral Instructions | ||||
|
For instructions 70 73 74 and 77 the address N is divided
into three groups: E the most significant bit corresponding to 512 x 2-19, P, the next five bits, and D, the remaining 4 bits. Values of D allocated to date are | ||||
| D = 1, | the Paper Tape Station | |||
| D = 2, | the Programme Control Register (see note below) | |||
| 70 N | a' = a + T, where T is the input from the device specified by D. | |||
| 73 N | a' = T, where T is the input from the device specified by D. | |||
| 74 N | This instruction causes the P bits to be sent to the peripheral controller specified by the E and D bits. It is used for devices which initiate autonomous data transfers, e.g. the magnetic tape controller. | |||
| 76 N | This instruction causes a program break, where N specifies the address at which the present programme is to be re-entered. | |||
| 77 N | n' = a, where a is to be output to the device specified by D. | |||
| Instructions 71 72 and 75 are not yet allocated. | ||||
| Note: | On the Programme Control Register | |||
| The content of this register, which is part of the programme control unit, is normally zero. After an instruction to the magnetic tape controller it may contain a series of ones corresponding to various error states (e.g. end of magnetic tape reached, but the interpretation of the bits can be defined as required). It also contains an indication of whether a given programme has been prevented from running; instructions 70 2 or 73 2 can be used to determine this, while instruction 77 2 can activate or inhibit a programme. | ||||
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Page created by Bill Purvis, last update: 20th November, 2003